The present invention relates to a semiconductor device having an electrode, such as a silicon bipolar transistor having an emitter electrode or an overlay type GaAs FET having a gate electrode, and a method of manufacturing the same.
Remarkable is the recent trend that high-frequency semiconductor devices having higher outputs are manufactured. For example, high-output silicon bipolar transistors (hereinafter called transistors) are manufactured by reducing a base width, forming a shallow active region, and micropatterning the pattern. The structure of a contact for an emitter electrode in a transistor greatly influences the characteristics and manufacture of the transistor, including micropatterning the pattern and short-circuiting between the emitter and base.
The structure of a contact for an emitter electrode in conventional transistors, and a method of manufacturing the same will be described with reference to FIGS. 1A and 1B, and FIGS. 2A and 2B. As shown in FIG. 1A, base region 4 is formed on the surface of silicon substrate 2. An element isolation region, an emitter resistor (neither are shown), and the like are also formed on substrate 2. SiO.sub.2 film 6 is formed on region 4, and etched by using a resist as a mask, making predetermined opening 8.
Phosphorus is diffused from a POCl.sub.3 mass, using film 6 as a mask, thereby forming emitter region 10. PtSi region 12 is formed in region 10 by annealing, in order to decrease a contact resistance. Then, as shown in FIG. 1B, Ti layer 16, Pt layer 18 and Au layer 20 are formed, sequentially one upon another, thereby preparing emitter electrode portion 14.
The width of region 10 can be reduced, to improve high-frequency characteristics are improved. Pt is diffused in an end portion (surrounded by circle 22 in FIG. 1B of region 10 during the forming of layer 12 or during the subsequent annealing. Layer 12 (or portion 14), therefore, tends to be easily short-circuited to base region 4, resulting in a defective product. This is more notable when region 10 is shallow for improving the transistor characteristics.
A second conventional structure of a semiconductor device wherein short-circuiting between layer 12 in region 10 and region 4 is prevented, and a method of manufacturing the device are shown in FIGS. 2A and 2B. The same reference numerals in FIGS. 2A and 2B denote the same portions as in FIGS. 1A and 1B, and a detailed description thereof will be omitted. "Overhang" silicon nitride film 24 is formed on film 6. SiO.sub.2 film 6 is overetched using film 24 as a mask, thereby forming opening 26. Emitter region 10 is formed in opening 26 using film 24 as a mask, and layer 12 for reducing the contact resistance is formed therein. Layers 16, 18 and 20 are formed sequentially on film 24, thereby preparing emitter electrode portion 14.
In the second structure, layer 12 and portion 14 are formed at part of the central portion of region 10 and not on a periphery thereof. Therefore, even if Pt is diffused in region 10 during the forming of layer 12 or during the subsequent annealing, it does not reach region 4, and portion 14 and region 4 will not be short-circuited. However, since film 24 is an "overhang", poor step coverage occurs in layer 16 of portion 14. Then, layers 18 and 20 formed on layer 16 contact region 10 through the poor step coverage portion and migrate into region 4, short-circuiting portion 14 and region 4 and degrading the characteristics of the device. To prevent this, opening 26 in film 6 is made larger by overetching, thereby enlarging region 10. In this case, however, the capacitance between regions 10 and 4 increases, inevitably decreasing a power gain and a cut-off frequency.